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» Designing a Memory Module Tester
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ISPASS
2003
IEEE
14 years 2 months ago
Performance study of a cluster runtime system for dynamic interactive stream-oriented applications
Emerging application domains such as interactive vision, animation, and multimedia collaboration display dynamic scalable parallelism, and high computational requirements, making ...
Arnab Paul, Nissim Harel, Sameer Adhikari, Bikash ...
AAAI
2006
13 years 10 months ago
Multimodal Cognitive Architecture: Making Perception More Central to Intelligent Behavior
I propose that the notion of cognitive state be broadened from the current predicate-symbolic, Language-of-Thought framework to a multi-modal one, where perception and kinesthetic...
B. Chandrasekaran
DATE
2009
IEEE
148views Hardware» more  DATE 2009»
14 years 3 months ago
A new design-for-test technique for SRAM core-cell stability faults
—Core-cell stability represents the ability of the core-cell to keep the stored data. With the rapid development of semiconductor memories, their test is becoming a major concern...
Alexandre Ney, Luigi Dilillo, Patrick Girard, Serg...
NOCS
2009
IEEE
14 years 3 months ago
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
Anh T. Tran, Dean Truong, Bevan M. Baas
TMC
2010
130views more  TMC 2010»
13 years 7 months ago
SYNAPSE++: Code Dissemination in Wireless Sensor Networks Using Fountain Codes
—This paper presents SYNAPSE++, a system for over the air reprogramming of wireless sensor networks (WSNs). In contrast to previous solutions, which implement plain negative ackn...
Michele Rossi, Nicola Bui, Giovanni Zanca, Luca St...