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IPPS
2002
IEEE
14 years 1 months ago
Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
VLSID
2002
IEEE
123views VLSI» more  VLSID 2002»
14 years 9 months ago
Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories
With the increased use of embedded/portable devices such as smart cellular phones, pagers, PDAs, hand-held computers, and CD players, improving energy efficiency is becoming a cri...
Victor Delaluz, Mahmut T. Kandemir, Narayanan Vija...
ISCAS
2002
IEEE
124views Hardware» more  ISCAS 2002»
14 years 1 months ago
Performance optimization of multiple memory architectures for DSP
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
ICVS
2001
Springer
14 years 1 months ago
A Real-Time Vision Module for Interactive Perceptual Agents
Interactive robotics demands real-time visual information about the environment. Real time vision processing, however, places a heavy load on the robot’s limited resources, and m...
Bruce A. Maxwell, Nathaniel Fairfield, Nikolas Joh...
AP2PC
2004
Springer
14 years 2 months ago
An Agent Module for a System on Mobile Devices
A Middleware is the software that assists an application to interact or communicate with other applications, networks, hardware, and/or operating systems. We have earlier proposed ...
Praveen Madiraju, Sushil K. Prasad, Rajshekhar Sun...