122 search results - page 8 / 25 » Designing a Memory Module Tester |
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
Abstract— This paper presents a six-transistor (6T) singleended static random access memory (SE-SRAM) bitcell with an isolated read-port, suitable for low-Î and low-power embedd...
IOLTS
2008
IEEE
14 years 3 months ago
2008
IEEE
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
ISPAN
1997
IEEE
14 years 1 months ago
1997
IEEE
The thesis of this research is that the task of exposing the parallelism in a given application should be left to the algorithm designer, who has intimate knowledge of the applica...
ICMCS
2008
IEEE
14 years 3 months ago
2008
IEEE
The efficient implementation of multimedia algorithms, for the ever increasing complexity of the specifications and the emergence of the new generation of processing platforms c...
ISVLSI
2008
IEEE
14 years 3 months ago
2008
IEEE
With the advent of nanometer technologies, the design size of integrated circuits is getting larger and the operation speed is getting faster. As a consequence, test cost is becom...