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PPOPP
2010
ACM
14 years 7 months ago
Modeling transactional memory workload performance
Transactional memory promises to make parallel programming easier than with fine-grained locking, while performing just as well. This performance claim is not always borne out bec...
Donald E. Porter, Emmett Witchel
ISPA
2005
Springer
14 years 3 months ago
Reducing the Overhead of Intra-Node Communication in Clusters of SMPs
Abstract. This article presents the C++ library vShark which reduces the intranode communication overhead of parallel programs on clusters of SMPs. The library is built on top of m...
Sascha Hunold, Thomas Rauber
CHARME
2001
Springer
117views Hardware» more  CHARME 2001»
14 years 2 months ago
A Higher-Level Language for Hardware Synthesis
We describe SAFL+: a call-by-value, parallel language in the style of ML which combines imperative, concurrent and functional programming. Synchronous channels allow communication ...
Richard Sharp, Alan Mycroft
PPOPP
1995
ACM
14 years 1 months ago
High Performance Synchronization Algorithms for Multiprogrammed Multiprocessors
Scalable busy-wait synchronization algorithms are essential for achieving good parallel program performance on large scale multiprocessors. Such algorithms include mutual exclusio...
Robert W. Wisniewski, Leonidas I. Kontothanassis, ...
IEEEPACT
2009
IEEE
13 years 7 months ago
Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor
Efficiently using the hardware capabilities of the Cell processor, a heterogeneous chip multiprocessor that uses several levels of parallelism to deliver high performance, and bei...
Tarik Saidani, Joel Falcou, Claude Tadonki, Lionel...