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ITC
1994
IEEE
151views Hardware» more  ITC 1994»
15 years 10 months ago
Automated Logic Synthesis of Random-Pattern-Testable Circuits
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
Nur A. Touba, Edward J. McCluskey
ASPLOS
1992
ACM
15 years 10 months ago
Efficient Superscalar Performance Through Boosting
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
Michael D. Smith, Mark Horowitz, Monica S. Lam
ASPDAC
2007
ACM
95views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Optimization of Arithmetic Datapaths with Finite Word-Length Operands
Abstract: This paper presents an approach to area optimization of arithmetic datapaths that perform polynomial computations over bit-vectors with finite widths. Examples of such de...
Sivaram Gopalakrishnan, Priyank Kalla, Florian Ene...
ASPDAC
2007
ACM
81views Hardware» more  ASPDAC 2007»
15 years 10 months ago
LEAF: A System Level Leakage-Aware Floorplanner for SoCs
Abstract-- Process scaling and higher leakage power have resulted in increased power densities and elevated die temperatures. Due to the interdependence of temperature and leakage ...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
CAV
2010
Springer
243views Hardware» more  CAV 2010»
15 years 10 months ago
libalf: The Automata Learning Framework
d Abstract) Benedikt Bollig1 , Joost-Pieter Katoen2 , Carsten Kern2 , Martin Leucker3 , Daniel Neider2 , and David R. Piegdon2 1 LSV, ENS Cachan, CNRS, 2 RWTH Aachen University, 3 ...
Benedikt Bollig, Joost-Pieter Katoen, Carsten Kern...