2945 search results - page 465 / 589 » Designing and Implementing Malicious Hardware |
142
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ISCA
1999
IEEE
15 years 10 months ago
1999
IEEE
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...
160
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ASAP
2007
IEEE
15 years 8 months ago
2007
IEEE
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
156
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based ...
179
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FPGA
2009
ACM
16 years 29 days ago
2009
ACM
Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA’s lo...
205
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FCCM
2008
IEEE
16 years 19 days ago
2008
IEEE
The map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped out...