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» Designing and Implementing Malicious Hardware
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IPPS
2003
IEEE
15 years 9 months ago
Experiences and Lessons Learned with a Portable Interface to Hardware Performance Counters
The PAPI project has defined and implemented a crossplatform interface to the hardware counters available on most modern microprocessors. The interface has gained widespread use ...
Jack Dongarra, Kevin S. London, Shirley Moore, Phi...
SASP
2009
IEEE
238views Hardware» more  SASP 2009»
15 years 10 months ago
Hardware acceleration of multi-view face detection
—This paper presents a parallelized architecture for hardware acceleration of multi-view face detection. In our architecture, the multi-view face detection system generates rotat...
Junguk Cho, Bridget Benson, Ryan Kastner
CHARME
2001
Springer
117views Hardware» more  CHARME 2001»
15 years 8 months ago
A Higher-Level Language for Hardware Synthesis
We describe SAFL+: a call-by-value, parallel language in the style of ML which combines imperative, concurrent and functional programming. Synchronous channels allow communication ...
Richard Sharp, Alan Mycroft
DATE
2005
IEEE
116views Hardware» more  DATE 2005»
15 years 9 months ago
Uniformly-Switching Logic for Cryptographic Hardware
Recent work on Differential Power Analysis shows that even mathematically-secure cryptographic protocols may be vulnerable at the physical implementation level. By measuring energ...
Igor L. Markov, Dmitri Maslov
139
Voted
FPL
2005
Springer
127views Hardware» more  FPL 2005»
15 years 9 months ago
Efficient Hardware Architectures for Modular Multiplication on FPGAs
The computational fundament of most public-key cryptosystems is the modular multiplication. Improving the efficiency of the modular multiplication is directly associated with the...
David Narh Amanor, Viktor Bunimov, Christof Paar, ...