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DATE
2004
IEEE
109views Hardware» more  DATE 2004»
15 years 8 months ago
RTL Processor Synthesis for Architecture Exploration and Implementation
Architecture description languages are widely used to perform architecture exploration for application-driven designs, whereas the RT-level is the commonly accepted level for hard...
Oliver Schliebusch, Anupam Chattopadhyay, Rainer L...
DCC
2007
IEEE
16 years 3 months ago
Algorithms and Hardware Structures for Unobtrusive Real-Time Compression of Instruction and Data Address Traces
Instruction and data address traces are widely used by computer designers for quantitative evaluations of new architectures and workload characterization, as well as by software de...
Milena Milenkovic, Aleksandar Milenkovic, Martin B...
GLOBECOM
2009
IEEE
15 years 11 months ago
Development Framework for Implementing FPGA-Based Cognitive Network Nodes
—This paper identifies important features a cognitive radio framework should provide, namely a virtual architecture ware abstraction, an adaptive run-time system for managing co...
Jorg Lotze, Suhaib A. Fahmy, Juanjo Noguera, Baris...
FPL
2009
Springer
117views Hardware» more  FPL 2009»
15 years 9 months ago
Data parallel FPGA workloads: Software versus hardware
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) ...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
SPAA
1990
ACM
15 years 8 months ago
Hardware Speedups in Long Integer Multiplication
We present various experiments in Hardware/Software designtradeoffs met in speeding up long integer multiplications. This work spans over a year, with more than 12 different hardw...
Mark Shand, Patrice Bertin, Jean Vuillemin