2945 search results - page 72 / 589 » Designing and Implementing Malicious Hardware |
142
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ISCAS
2005
IEEE
15 years 10 months ago
2005
IEEE
—This paper presents a SoC platform based design for the implementation of AAC audio decoder. We present the approach not only for the characteristics of the algorithm, but also ...
182
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CODES
2002
IEEE
15 years 9 months ago
2002
IEEE
The aggressive evolution of the semiconductor industry — smaller process geometries, higher densities, and greater chip complexity — has provided design engineers the means to...
183
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RTAS
1997
IEEE
15 years 8 months ago
1997
IEEE
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
134
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ERSA
2008
15 years 5 months ago
2008
This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MC-FPGAs). Conventional MC-FPGAs use dedicated tracks...
134
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ASAP
2006
IEEE
15 years 6 months ago
2006
IEEE
This paper proposes a novel parallel approach for pipelining of nested multiplexer loops to design high speed decision feedback equalizers (DFEs) based on look-ahead techniques. I...