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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 23 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
TSD
2010
Springer
13 years 5 months ago
Embedded Speech Recognition in UPnP (DLNA) Environment
In the past decade great technological advances have been made in internet services, personal computers, telecommunications, media and entertainment. Many of these advances have be...
Jozef Ivanecký, Radek Hampl
ICPR
2004
IEEE
14 years 8 months ago
From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers
Parallel processors such as SIMD computers have been successfully used in various areas of high performance image and data processing. Due to their characteristics of highly regula...
Jie Han, Pieter Jonker
PRL
2010
158views more  PRL 2010»
13 years 6 months ago
Data clustering: 50 years beyond K-means
: Organizing data into sensible groupings is one of the most fundamental modes of understanding and learning. As an example, a common scheme of scientific classification puts organ...
Anil K. Jain
SOSP
2007
ACM
14 years 4 months ago
Sinfonia: a new paradigm for building scalable distributed systems
We propose a new paradigm for building scalable distributed systems. Our approach does not require dealing with message-passing protocols—a major complication in existing distri...
Marcos Kawazoe Aguilera, Arif Merchant, Mehul A. S...