84 search results - page 7 / 17 » Designing and testing fault-tolerant techniques for SRAM-bas... |
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan c...
DAC
2009
ACM
14 years 9 months ago
2009
ACM
Silicon nanowires are a promising solution to address the increasing challenges of fabrication and design at the future nodes of the Complementary Metal-Oxide-Semiconductor (CMOS)...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
CASES
2009
ACM
14 years 1 months ago
2009
ACM
Nanowire crossbar circuits are an emerging architectural paradigm that promises a higher integration density and an improved fault-tolerance due to its reconfigurability. In this...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...