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IPPS
2005
IEEE
14 years 2 months ago
Runtime Empirical Selection of Loop Schedulers on Hyperthreaded SMPs
Hyperthreaded (HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by e...
Yun Zhang, Michael Voss
ISCAS
2005
IEEE
209views Hardware» more  ISCAS 2005»
14 years 2 months ago
Low complexity H.263 to H.264 video transcoding using motion vector decomposition
The H.264 adopts various block types and multiple reference frames for motion compensation. For transcoding a video sequence from the H.263 format to the H.264 format, it is benef...
Kai-Tat Fung, Wan-Chi Siu
ISPAN
2005
IEEE
14 years 2 months ago
Process Scheduling for the Parallel Desktop
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...
Eitan Frachtenberg
ISPASS
2005
IEEE
14 years 2 months ago
BioBench: A Benchmark Suite of Bioinformatics Applications
Recent advances in bioinformatics and the significant increase in computational power available to researchers have made it possible to make better use of the vast amounts of gene...
Kursad Albayraktaroglu, Aamer Jaleel, Xue Wu, Mano...
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
14 years 2 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...