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» Designing floating codes for expected performance
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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 7 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
CODES
2007
IEEE
14 years 1 months ago
On the impact of manufacturing process variations on the lifetime of sensor networks
As an emerging technology, sensor networks provide the ability to accurately monitor the characteristics of wide geographical areas over long periods of time. The lifetime of indi...
Siddharth Garg, Diana Marculescu
CIARP
2008
Springer
13 years 9 months ago
On the Complementarity of Face Parts for Gender Recognition
This paper evaluates the expected complementarity between the most prominent parts of the face for the gender recognition task. Given the image of a face, five important parts (rig...
Yasmina Andreu, Ramón Alberto Mollineda
TVLSI
2010
13 years 2 months ago
Architectural Enhancement and System Software Support for Program Code Integrity Monitoring in Application-Specific Instruction-
Program code in a computer system can be altered either by malicious security attacks or by various faults in microprocessors. At the instruction level, all code modifications are ...
Hai Lin, Yunsi Fei, Xuan Guan, Zhijie Jerry Shi
DAC
2007
ACM
14 years 8 months ago
Energy-Aware Data Compression for Multi-Level Cell (MLC) Flash Memory
We discover significant value-dependent programming energy variations in multi-level cell (MLC) flash memories, and introduce an energy-aware data compression method that minimize...
Yongsoo Joo, Youngjin Cho, Donghwa Shin, Naehyuck ...