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» Designing for Xilinx XC6200 FPGAs
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EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
13 years 11 months ago
A hardware environment for prototyping and partitioning based on multiple FPGAs
This paper presents a multiple-FPGA-based experimentation board. The problem to be solved is that of implementing a circuit into a set of FPGAs. This board provides a hardware env...
Marc Wendling, Wolfgang Rosenstiel
FPL
2003
Springer
259views Hardware» more  FPL 2003»
14 years 25 days ago
Branch Optimisation Techniques for Hardware Compilation
Abstract. This paper explores using information about program branch probabilities to optimise reconfigurable designs. The basic premise is to promote utilization by dedicating mo...
Henry Styles, Wayne Luk
FCCM
2008
IEEE
160views VLSI» more  FCCM 2008»
14 years 2 months ago
Facilitating Processor-Based DPR Systems for non-DPR Experts
Currently, only Xilinx Field Programmable Gate Arrays (FPGAs) support Dynamic Partial Reconfiguration (DPR). While there is currently some Computer Aided Design (CAD) tool support...
Edward Chen, William A. Gruver, Dorian Sabaz, Lesl...
PDPTA
2000
13 years 9 months ago
Constant Multipliers for FPGAs
This paper presents a survey of techniques to implement multiplications by constants on FPGAs. It shows in particular that a simple and well-known technique, canonical signed recod...
Florent de Dinechin, Vincent Lefèvre
FPL
2000
Springer
124views Hardware» more  FPL 2000»
13 years 11 months ago
Balancing Logic Utilization and Area Efficiency in FPGAs
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
Russell Tessier, Heather Giza