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» Designing for Xilinx XC6200 FPGAs
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RSP
2003
IEEE
149views Control Systems» more  RSP 2003»
14 years 27 days ago
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA
In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures a...
Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cav...
CDES
2006
158views Hardware» more  CDES 2006»
13 years 9 months ago
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia
ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
14 years 4 months ago
Application-specific customization of parameterized FPGA soft-core processors
Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are p...
David Sheldon, Rakesh Kumar, Roman L. Lysecky, Fra...
ERSA
2006
91views Hardware» more  ERSA 2006»
13 years 9 months ago
Intrinsic Embedded Hardware Evolution of Block-based Neural Networks
- An intrinsic embedded online evolution system has been designed using Block-based neural networks and implemented on Xilinx VirtexIIPro FPGAs. The designed network can dynamicall...
Saumil Merchant, Gregory D. Peterson, Seong Kong
FPGA
2004
ACM
180views FPGA» more  FPGA 2004»
14 years 1 months ago
A VHDL MPEG-7 shape descriptor extractor
Unlike its predecessors, MPEG-7 standardizes multimedia metadata description. By providing robust descriptors and an effective system for storing them, MPEG-7 is designed to provi...
Bret Woz, Andreas E. Savakis