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EUROSYS
2007
ACM
16 years 1 months ago
Latency and bandwidth-minimizing failure detectors
Failure detectors are fundamental building blocks in distributed systems. Multi-node failure detectors, where the detector is tasked with monitoring N other nodes, play a critical...
Kelvin C. W. So, Emin Gün Sirer
ICCAD
2008
IEEE
108views Hardware» more  ICCAD 2008»
16 years 1 months ago
FBT: filled buffer technique to reduce code size for VLIW processors
— VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated...
Talal Bonny, Jörg Henkel
ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
16 years 1 months ago
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
Shiyan Hu, Zhuo Li, Charles J. Alpert
ICCAD
2006
IEEE
149views Hardware» more  ICCAD 2006»
16 years 1 months ago
Thermal sensor allocation and placement for reconfigurable systems
Temperature monitoring using thermal sensors is an essential tool for evaluating the thermal behavior and sustaining the reliable operation in high-performance and high-power syst...
Rajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci...
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
16 years 1 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
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