FBT: filled buffer technique to reduce code size for VLIW processors

— VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated code size of the compiled application code. Therefore, reducing the application code size is a design key issue for VLIW processors. In this paper we adapt a hardware-supported approach called “Deflate” [12] which has been used before in data compression. It can significantly reduce the code size compared to state-of-theart approaches for VLIW processors as we will show within this work. In fact, we enhance the “Deflate” algorithm by using a new technique called Filled Buffer Technique which can be applied to any Lempel-Ziv family algorithms to improve compression ratio in average by more than 13% compared to the sole “Deflate” algorithm. Using our Filled Buffer Technique in conjunction with “V2F” [15] improves the compression ratio by 10%. We have conducted evaluations using a representa...

• Type: Conference
• Year: 2008
• Where: ICCAD
• Authors: Talal Bonny, Jörg Henkel
• Keywords: Bloated Code Size, Compression Ratio, Hardware, ICCAD 2008, VLIW Processors