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» Designing hardware with dynamic memory abstraction
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ANCS
2007
ACM
14 years 16 days ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos
CGA
2008
13 years 8 months ago
Mobile 3D City Maps
ion and abstraction. By the end of the 20th century, technology had advanced to the point where computerized methods had revolutionized surveying and mapmaking practices. Now, the ...
Antti Nurminen
CLUSTER
2008
IEEE
14 years 3 months ago
Reliable adaptable Network RAM
Abstract—We present reliability solutions for adaptable Network RAM systems running on general-purpose clusters. Network RAM allows nodes with over-committed memory to swap pages...
Tia Newhall, Daniel Amato, Alexandr Pshenichkin
ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
14 years 5 months ago
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
Shiyan Hu, Zhuo Li, Charles J. Alpert
DATE
2010
IEEE
157views Hardware» more  DATE 2010»
14 years 1 months ago
RMOT: Recursion in model order for task execution time estimation in a software pipeline
Abstract—This paper addresses the problem of execution time estimation for tasks in a software pipeline independent of the application structure or the underlying architecture. A...
Nabeel Iqbal, M. A. Siddique, Jörg Henkel