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IESS
2007
Springer
120views Hardware» more  IESS 2007»
14 years 2 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
ECRTS
2006
IEEE
14 years 2 months ago
The Dependency Management Framework: A Case Study of the ION CubeSat
Due to the complexity and requirements of modern realtime systems, multiple teams must often work concurrently and independently to develop the various components of the system. S...
Hui Ding, Leon Arber, Lui Sha, Marco Caccamo
ICRA
2006
IEEE
117views Robotics» more  ICRA 2006»
14 years 2 months ago
A Neurally Controlled Robot Competes and Cooperates with Humans in Segway Soccer
— A new RoboCup soccer league is being developed, focusing on human-robot interaction. In this league each team consists of both a human player, mounted on a Segway HT scooter, a...
Jason Fleischer, Botond Szatmáry, Donald Hu...
IPCCC
2006
IEEE
14 years 2 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
CASES
2006
ACM
14 years 2 months ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh
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