31 search results - page 2 / 7 » Designing packet buffers for router linecards |
ANCS
2007
ACM
13 years 11 months ago
2007
ACM
We propose a distributed congestion management scheme for non-blocking, 3-stage Clos networks, comprising plain buffered crossbar switches. VOQ requests are routed using multipath...
TC
2008
13 years 7 months ago
2008
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
SIGCOMM
2003
ACM
14 years 20 days ago
2003
ACM
Routers built around a single-stage crossbar and a centralized scheduler do not scale, and (in practice) do not provide the throughput guarantees that network operators need to ma...
MICRO
2003
IEEE
14 years 21 days ago
2003
IEEE
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...
ANCS
2007
ACM
13 years 11 months ago
2007
ACM
Recent theoretical results in buffer sizing research suggest that core Internet routers can achieve high link utilization, if they are capable of storing only a handful of packets...