1226 search results - page 24 / 246 » Designing systems-on-chip using cores |
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
- This paper aims at discussing the implementation of simulation systems for SNN based on analog computation cores (neuromimetic ICs). Such systems are an alternative to completely...
VTS
2000
IEEE
14 years 3 days ago
2000
IEEE
A novel design-for-test (DFT) technique is presented for designing a core with a “virtual scan chain” which looks (to the system integrator) like it is shorter than the real s...
ERSA
2006
13 years 9 months ago
2006
- This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area,...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the e...
JSSPP
2001
Springer
14 years 5 days ago
2001
Springer
The Maui scheduler has received wide acceptance in the HPC community as a highly configurable and effective batch scheduler. It is currently in use on hundreds of SP, O2K, and Li...