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ASPLOS
2010
ACM
14 years 2 months ago
Specifying and dynamically verifying address translation-aware memory consistency
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation (AT) systems. Detecting bugs and faults requires a clear speciļ...
Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. So...
ITC
2003
IEEE
157views Hardware» more  ITC 2003»
14 years 27 days ago
Parity-Based Concurrent Error Detection in Symmetric Block Ciphers
Deliberate injection of faults into cryptographic devices is an effective cryptanalysis technique against symmetric and asymmetric encryption. We will describe a general concurren...
Ramesh Karri, Grigori Kuznetsov, Michael Göss...
GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
14 years 18 days ago
Protected IP-core test generation
Design simpliļ¬cation is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi
GLOBECOM
2009
IEEE
13 years 11 months ago
Experimental Validation of Periodic Codes for PON Monitoring
In this paper we investigate both experimentally and via simulation the monitoring of fiber link quality in a PON using optical coding technology. We use a new, simple and costeffe...
Mohammad M. Rad, Habib Fathallah, Sophie LaRochell...
MICRO
2009
IEEE
178views Hardware» more  MICRO 2009»
14 years 2 months ago
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerso...