Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
Background: Although protein-protein interaction networks determined with high-throughput methods are incomplete, they are commonly used to infer the topology of the complete inte...
Abstract—On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its to...
Abstract--We consider using traceroute-like end-to-end measurement to infer the underlay topology for a group of hosts. One major issue is the measurement cost. Given hosts in an a...
Xing Jin, Wai-Pun Ken Yiu, S.-H. Gary Chan, Yajun ...
—We study throughput-optimal scheduling/routing over mobile ad-hoc networks with time-varying (fading) channels. Traditional back-pressure algorithms (based on the work by Tassiu...