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INFOCOM
2002
IEEE
14 years 14 days ago
Joint Scheduling and Power Control for Wireless Ad-hoc Networks
—In this paper, we introduce a cross-layer design framework to the multiple access problem in contention-based wireless ad hoc networks. The motivation for this study is twofold,...
Tamer A. ElBatt, Anthony Ephremides
ICCD
2007
IEEE
99views Hardware» more  ICCD 2007»
13 years 11 months ago
Power reduction of chip multi-processors using shared resource control cooperating with DVFS
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...
Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Tak...
DAC
2005
ACM
14 years 8 months ago
User-perceived latency driven voltage scaling for interactive applications
Power has become a critical concern for battery-driven computing systems, on which many applications that are run are interactive. System-level voltage scaling techniques, such as...
Le Yan, Lin Zhong, Niraj K. Jha
VLSID
2003
IEEE
134views VLSI» more  VLSID 2003»
14 years 8 months ago
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
Saraju P. Mohanty, N. Ranganathan
FPGA
2003
ACM
167views FPGA» more  FPGA 2003»
14 years 23 days ago
A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology
This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...
Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, R...