73 search results - page 3 / 15 » Deterministic Logic BIST for Transition Fault Testing |
VTS
1997
IEEE
13 years 12 months ago
1997
IEEE
Despite all of the advantages that circular BIST ofsers compared to conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion, it has se...
TVLSI
2002
13 years 7 months ago
2002
Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simp...
IOLTS
2006
IEEE
14 years 1 months ago
2006
IEEE
— Delay failures are becoming a dominant failure mechanism in nanometer technologies. Diagnosis of such failures is important to ensure yield and robustness of the design. Howeve...
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...
DSD
2005
IEEE
13 years 9 months ago
2005
IEEE
Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of f...