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ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
14 years 2 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
14 years 2 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock
KBSE
2005
IEEE
14 years 2 months ago
Automated test generation for engineering applications
In test generation based on model-checking, white-box test criteria are represented as trap conditions written in a temporal logic. A model checker is used to refute trap conditio...
Songtao Xia, Ben Di Vito, César Muño...
STEP
2005
IEEE
14 years 2 months ago
Using Metamodels in Service Interoperability
Interoperability in service oriented environments is heavily inuenced by the view that the cooperating services have on their data. e term service for the abstract contract concl...
Andreas Winter, Jürgen Ebert
ACMSE
2005
ACM
14 years 2 months ago
The bipartite clique: a topological paradigm for WWWeb user search customization
Web user search customization research has been fueled by the recognition that if the WWW is to attain to its optimal potential as an interactive medium the development of new and...
Brenda F. Miles, Vir V. Phoha
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