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» Device and Technology Challenges for Nanoscale CMOS
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IEICET
2006
79views more  IEICET 2006»
13 years 9 months ago
System LSI: Challenges and Opportunities
End of CMOS scaling has been discussed in many places since the late 90's. Even if the end of CMOS scaling is irrelevant, it is for sure that we are facing a turning point in...
Tadahiro Kuroda
MICRO
2008
IEEE
142views Hardware» more  MICRO 2008»
14 years 3 months ago
NBTI tolerant microarchitecture design in the presence of process variation
—Negative bias temperature instability (NBTI), which reduces the lifetime of PMOS transistors, is becoming a growing reliability concern for sub-micrometer CMOS technologies. Par...
Xin Fu, Tao Li, José A. B. Fortes
CORR
2008
Springer
92views Education» more  CORR 2008»
13 years 8 months ago
Interconnect Challenges in Highly Integrated MEMS/ASIC Subsystems
Micromechanical devices like accelerometers or rotation sensors form an increasing segment beneath the devices supplying the consumer market. A hybrid integration approach to buil...
N. Marenco, S. Warnat, W. Reinert
GLVLSI
2008
IEEE
120views VLSI» more  GLVLSI 2008»
14 years 3 months ago
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Novel nano-scale devices have shown promising potential to overcome physical barriers faced by complementary metaloxide semiconductor (CMOS) technology in future circuit design. H...
Yexin Zheng, Michael S. Hsiao, Chao Huang
DAC
2005
ACM
14 years 10 months ago
Designing logic circuits for probabilistic computation in the presence of noise
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...