410 search results - page 49 / 82 » Diagonal routing in high performance microprocessor design |
JCP
2008
13 years 11 months ago
2008
An important issues in the design of interconnection networks for massively parallel computers is scalability. A new scalable interconnection network topology, called Double-Loop H...
MICRO
2007
IEEE
14 years 5 months ago
2007
IEEE
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
DATE
2007
IEEE
14 years 5 months ago
2007
IEEE
Future microprocessors will be highly susceptible to transient errors as the sizes of transistors decrease due to CMOS scaling. Prior techniques advocated full scale structural or...
EH
2004
IEEE
14 years 2 months ago
2004
IEEE
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
SIGCOMM
2005
ACM
14 years 4 months ago
2005
ACM
This paper describes ExOR, an integrated routing and MAC protocol that increases the throughput of large unicast transfers in multi-hop wireless networks. ExOR chooses each hop of...