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» Diagonal routing in high performance microprocessor design
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HIS
2009
13 years 5 months ago
Design Methodology of a Fault Aware Controller Using an Incipient Fault Diagonizer
The problem of failure diagnosis has received a considerable attention in the domain of reliability engineering, process control and computer science. The increasing stringent req...
Joydeb Roychoudhury, Tribeni Prasad Banerjee, Anup...
ITCC
2005
IEEE
14 years 28 days ago
A RDT-Based Interconnection Network for Scalable Network-on-Chip Designs
The interconnection network plays an important role in the performance and energy consumption of a Networkon-Chip (NoC) system. In this paper, we propose a RDT(2,2,1)/α-based int...
Yang Yu, Mei Yang, Yulu Yang, Yingtao Jiang
ISQED
2007
IEEE
160views Hardware» more  ISQED 2007»
14 years 1 months ago
On-Chip Inductance in X Architecture Enabled Design
The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition tim...
Santosh Shah, Arani Sinha, Li Song, Narain D. Aror...
ICCAD
2002
IEEE
154views Hardware» more  ICCAD 2002»
14 years 4 months ago
Concurrent flip-flop and repeater insertion for high performance integrated circuits
For many years, CMOS process scaling has allowed a steady increase in the operating frequency and integration density of integrated circuits. Only recently, however, have we reach...
Pasquale Cocchini
ASPDAC
2004
ACM
149views Hardware» more  ASPDAC 2004»
14 years 23 days ago
A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design
With the exponential reduction in the scaling of feature size, inter-wire coupling capacitance becomes the dominant part of load capacitance. Two problems are introduced by coupli...
Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, J...