35 search results - page 3 / 7 » Die Stacking (3D) Microarchitecture |
ICCAD
2009
IEEE
13 years 6 months ago
2009
IEEE
Pre-bond testing of 3D stacked ICs involves testing individual dies before bonding. The overall yield of 3D ICs improves with prebond testability because designers can avoid stack...
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
GLVLSI
2006
IEEE
14 years 2 months ago
2006
IEEE
3-dimensional integrated circuit (3D IC) technology places circuit blocks in the vertical dimension in addition to the conventional horizontal plane. Compared to conventional plan...
ICCD
2007
IEEE
14 years 5 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
VLSID
2010
IEEE
13 years 7 months ago
2010
IEEE
Due to the inherent nature of heat flow in 3D integrated circuits, stacked dies exhibit a wide range of thermal characteristics. The strong dependence of leakage with temperature...