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DATE
2010
IEEE
131views Hardware» more  DATE 2010»
14 years 19 days ago
Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits
Abstract—This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultr...
Armin Tajalli, Yusuf Leblebici
DFT
2002
IEEE
121views VLSI» more  DFT 2002»
14 years 15 days ago
Testing Digital Circuits with Constraints
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of l...
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McC...
ISQED
2006
IEEE
153views Hardware» more  ISQED 2006»
14 years 1 months ago
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two...
Chong Zhao, Sujit Dey
DATE
1997
IEEE
95views Hardware» more  DATE 1997»
13 years 11 months ago
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications
A design methodology for the synthesis of digital circuits used in high throughput digital modems is presented. The methodology spans digital modem design from the link level to t...
Patrick Schaumont, Serge Vernalde, Luc Rijnders, M...
CEC
2003
IEEE
13 years 11 months ago
A modified ant colony algorithm for evolutionary design of digital circuits
Evolutionary computation presents a new paradigm shift in hardware design and synthesis. According to this paradigm, hardware design is pursued by deriving inspiration from biologi...
Mostafa Abd-El-Barr, Sadiq M. Sait, Bambang A. B. ...