Sciweavers

787 search results - page 121 / 158
» Digital Algebra and Circuits
Sort
View
ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
14 years 28 days ago
A novel improvement technique for high-level test synthesis
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jaha...
GECCO
2003
Springer
120views Optimization» more  GECCO 2003»
14 years 26 days ago
Multi-FPGA Systems Synthesis by Means of Evolutionary Computation
Abstract. Multi-FPGA systems (MFS) are used for a great variety of applications, for instance, dynamically re-configurable hardware applications, digital circuit emulation, and num...
José Ignacio Hidalgo, Francisco Ferná...
ASP
2001
Springer
14 years 4 days ago
Answer Set Programming and Bounded Model Checking
In this paper bounded model checking of asynchronous concurrent systems is introduced as a promising application area for answer set programming. This is an extension of earlier w...
Keijo Heljanko, Ilkka Niemelä
FPL
1999
Springer
103views Hardware» more  FPL 1999»
13 years 12 months ago
IP Validation for FPGAs Using Hardware Object Technology
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional ...
Steve Casselman, John Schewel, Christophe Beaumont
ASYNC
1998
IEEE
71views Hardware» more  ASYNC 1998»
13 years 12 months ago
Towards Asynchronous A-D Conversion
Analogue to digital (A-D) converters with a xed conversion time are subject to errors due to metastability. These errors will occur in all converter designs with a bounded time fo...
D. J. Kinniment, Alexandre Yakovlev, Fei Xia, B. G...