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ASPDAC
2010
ACM
161views Hardware» more  ASPDAC 2010»
13 years 5 months ago
A dual-MST approach for clock network synthesis
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangel...
DAC
2009
ACM
13 years 5 months ago
A physical unclonable function defined using power distribution system equivalent resistance variations
For hardware security applications, the availability of secret keys is a critical component for secure activation, IC authentication and for other important applications including...
Ryan Helinski, Dhruva Acharyya, Jim Plusquellic
TC
2011
13 years 2 months ago
An Architecture for Fault-Tolerant Computation with Stochastic Logic
—Mounting concerns over variability, defects and noise motivate a new approach for digital circuitry: stochastic logic, that is to say, logic that operates on probabilistic signa...
Weikang Qian, Xin Li, Marc D. Riedel, Kia Bazargan...
ISPD
2009
ACM
141views Hardware» more  ISPD 2009»
14 years 2 months ago
A faster approximation scheme for timing driven minimum cost layer assignment
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
Shiyan Hu, Zhuo Li, Charles J. Alpert
FPGA
2009
ACM
159views FPGA» more  FPGA 2009»
14 years 2 months ago
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the inte...
Raphael Rubin, André DeHon