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» Dimensionality reduction and generalization
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DAC
2008
ACM
15 years 5 months ago
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
Min Ni, Seda Ogrenci Memik
BMCBI
2007
134views more  BMCBI 2007»
15 years 4 months ago
A framework for significance analysis of gene expression data using dimension reduction methods
Background: The most popular methods for significance analysis on microarray data are well suited to find genes differentially expressed across predefined categories. However, ide...
Lars Halvor Gidskehaug, Endre Anderssen, Arnar Fla...
CASON
2010
IEEE
14 years 7 months ago
Social Network Reduction Based on Stability
—The analysis of social networks is concentrated especially on uncovering hidden relations and properties of network members (vertices). Most of the current approaches are focuse...
Milos Kudelka, Zdenek Horak, Václav Sn&aacu...
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
16 years 21 days ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
EMSOFT
2005
Springer
15 years 9 months ago
A sink-n-hoist framework for leakage power reduction
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts have tried to integrate architecture...
Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee