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» Dimensions in program synthesis
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DATE
2000
IEEE
94views Hardware» more  DATE 2000»
14 years 2 months ago
Shared Memory Implementations of Synchronous Dataflow Specifications
There has been a proliferation of block-diagram environments for specifying and prototyping DSP systems. These include tools from academia like Ptolemy [3], and GRAPE [7], and com...
Praveen K. Murthy, Shuvra S. Bhattacharyya
ICSM
1997
IEEE
14 years 2 months ago
Software Change Through Design Maintenance
Conventional software engineering tends to focus on a small part of the software life cycle: the design and implementation of a product. The bulk of the lifetime cost is in the ma...
Ira D. Baxter, Christopher Pidgeon
MICRO
1994
IEEE
85views Hardware» more  MICRO 1994»
14 years 2 months ago
A high-performance microarchitecture with hardware-programmable functional units
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Throu...
Rahul Razdan, Michael D. Smith
FPGA
1992
ACM
176views FPGA» more  FPGA 1992»
14 years 1 months ago
Minimization of Permuted Reed-Muller Trees for Cellular Logic
The new family of Field Programmable Gate Arrays, CLI6000 from Concurrent Logic Inc realizes the truly Cellular Logic. It has been mainly designed for the realization of data path...
Li-Fei Wu, Marek A. Perkowski
ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
14 years 1 months ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...