956 search results - page 163 / 192 » Dimensions in program synthesis |
ISPD
2009
ACM
14 years 4 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
MODELS
2009
Springer
14 years 4 months ago
2009
Springer
Product line engineering is an emerging paradigm of developing a family of products. While product line analysis and design mainly focus on reasoning about commonality and variabi...
AGTIVE
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. In runtime monitoring, a programmer specifies code to execute whenever a sequence of events occurs during program execution. Previous and related work has shown that runt...
ASE
2005
13 years 9 months ago
2005
Techniques for efficiently evaluating future time Linear Temporal Logic (abbreviated LTL) formulae on finite execution traces are presented. While the standard models of LTL are i...
MICRO
2002
IEEE
14 years 2 months ago
2002
IEEE
Pre-execution attacks cache misses for which conventional address-prediction driven prefetching is ineffective. In pre-execution, copies of cache miss computations are isolated fr...