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CODES
2007
IEEE
14 years 4 months ago
HW/SW co-design for Esterel processing
We present a co-synthesis approach that accelerates reactive software processing by moving the calculation of complex expressions into external combinational hardware. The startin...
Sascha Gädtke, Claus Traulsen, Reinhard von H...
ISCA
2007
IEEE
152views Hardware» more  ISCA 2007»
14 years 4 months ago
Carbon: architectural support for fine-grained parallelism on chip multiprocessors
Chip multiprocessors (CMPs) are now commonplace, and the number of cores on a CMP is likely to grow steadily. However, in order to harness the additional compute resources of a CM...
Sanjeev Kumar, Christopher J. Hughes, Anthony D. N...
ASPDAC
2005
ACM
97views Hardware» more  ASPDAC 2005»
14 years 3 months ago
Opportunities and challenges for better than worst-case design
The progressive trend of fabrication technologies towards the nanometer regime has created a number of new physical design challenges for computer architects. Design complexity, u...
Todd M. Austin, Valeria Bertacco, David Blaauw, Tr...
IUI
2005
ACM
14 years 3 months ago
How to wreck a nice beach you sing calm incense
A principal problem in speech recognition is distinguishing between words and phrases that sound similar but have different meanings. Speech recognition programs produce a list of...
Henry Lieberman, Alexander Faaborg, Waseem Daher, ...
CODES
2003
IEEE
14 years 3 months ago
Design space minimization with timing and code size optimization for embedded DSP
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-M...