38 search results - page 3 / 8 » Direct synthesis of timed asynchronous circuits |
TCAD
2002
13 years 6 months ago
2002
ICCD
1999
IEEE
13 years 11 months ago
1999
IEEE
ions", in IEEE Transactions on CAD of VLSI, 25(3):403-412, March, 2006. , E. Mercer, C. Myers, "Modular Verification of Timed Systems Using Automatic Abstraction" in...
DSD
2010
IEEE
13 years 4 months ago
2010
IEEE
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementati...
ASYNC
2003
IEEE
14 years 5 days ago
2003
IEEE
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...