315 search results - page 35 / 63 » Disk layout optimization for reducing energy consumption |
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
WINET
2010
13 years 6 months ago
2010
Abstract In this work we study the combination of multicost routing and adjustable transmission power in wireless ad hoc networks, so as to obtain dynamic energy- and interference-...
IPCCC
2006
IEEE
14 years 1 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
CLUSTER
2007
IEEE
13 years 11 months ago
2007
IEEE
High-performance computing (HPC) systems consume a significant amount of power, resulting in high operational costs, reduced reliability, and wasting of natural resources. Therefor...