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ICCAD
2009
IEEE
151views Hardware» more  ICCAD 2009»
13 years 7 months ago
Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...
Mohit Gupta, Kwangok Jeong, Andrew B. Kahng
IDC
2009
Springer
13 years 7 months ago
Efficient Broadcasting by Selective Forwarding
A major challenge faced in mobile ad hoc networks (MANETs) is locating devices for communication, especially in the case of high node mobility and sparse node density. Present solu...
Doina Bein, Ajoy Kumar Datta, Balaji Ashok Sathyan...
IEEEPACT
2009
IEEE
13 years 7 months ago
Cache Sharing Management for Performance Fairness in Chip Multiprocessors
Resource sharing can cause unfair and unpredictable performance of concurrently executing applications in Chip-Multiprocessors (CMP). The shared last-level cache is one of the mos...
Xing Zhou, Wenguang Chen, Weimin Zheng
IEEEPACT
2009
IEEE
13 years 7 months ago
Adaptive Locks: Combining Transactions and Locks for Efficient Concurrency
Transactional memory is being advanced as an alternative to traditional lock-based synchronization for concurrent programming. Transactional memory simplifies the programming mode...
Takayuki Usui, Reimer Behrends, Jacob Evans, Yanni...
COMCOM
2010
167views more  COMCOM 2010»
13 years 7 months ago
Effective load for flow-level performance modelling of file transfers in wireless LANs
Today, a wide range of 802.11-based Wireless LANs (WLANs) have become dominant to provide wireless Internet access for file transfers. For engineering purposes, there is a need fo...
Geert Jan Hoekstra, Robert D. van der Mei
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