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HPCA
2012
IEEE
12 years 5 months ago
Improving write operations in MLC phase change memory
Phase change memory (PCM) recently has emerged as a promising technology to meet the fast growing demand for large capacity memory in modern computer systems. In particular, multi...
Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang 0002, B...
GIS
2007
ACM
14 years 11 months ago
Evacuation route planning: scalable heuristics
Given a transportation network, a vulnerable population, and a set of destinations, evacuation route planning identifies routes to minimize the time to evacuate the vulnerable pop...
Sangho Kim, Betsy George, Shashi Shekhar
HPCA
2007
IEEE
14 years 10 months ago
Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling
Performance gains in memory have traditionally been obtained by increasing memory bus widths and speeds. The diminishing returns of such techniques have led to the proposal of an ...
Brinda Ganesh, Aamer Jaleel, David Wang, Bruce L. ...
MOBIHOC
2007
ACM
14 years 9 months ago
Cross-layer latency minimization in wireless networks with SINR constraints
Recently, there has been substantial interest in the design of crosslayer protocols for wireless networks. These protocols optimize certain performance metric(s) of interest (e.g....
Deepti Chafekar, V. S. Anil Kumar, Madhav V. Marat...
ICCAD
2007
IEEE
118views Hardware» more  ICCAD 2007»
14 years 7 months ago
Timing variation-aware high-level synthesis
—This work proposes a new yield computation technique dedicated to HLS, which is an essential component in timing variationaware HLS research field. The SSTAs used by the curren...
Jongyoon Jung, Taewhan Kim