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» Distributed Synthesis for Well-Connected Architectures
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IEEEPACT
2008
IEEE
14 years 1 months ago
The PARSEC benchmark suite: characterization and architectural implications
This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). Prev...
Christian Bienia, Sanjeev Kumar, Jaswinder Pal Sin...
ISOLA
2010
Springer
13 years 5 months ago
Towards an Architecture for Runtime Interoperability
Abstract. Interoperability remains a fundamental challenge when connecting heterogeneous systems which encounter and spontaneously communicate with one another in pervasive computi...
Amel Bennaceur, Gordon S. Blair, Franck Chauvel, G...
DAC
2003
ACM
14 years 8 months ago
Automated synthesis of efficient binary decoders for retargetable software toolkits
A binary decoder is a common component of software development tools such as instruction set simulators, disassemblers and debuggers. The efficiency of the decoder can have a sign...
Wei Qin, Sharad Malik
ASPDAC
2006
ACM
148views Hardware» more  ASPDAC 2006»
13 years 11 months ago
TAPHS: thermal-aware unified physical-level and high-level synthesis
Thermal effects are becoming increasingly important during integrated circuit design. Thermal characteristics influence reliability, power consumption, cooling costs, and performan...
Zhenyu (Peter) Gu, Yonghong Yang, Jia Wang, Robert...
ICCAD
1998
IEEE
109views Hardware» more  ICCAD 1998»
13 years 11 months ago
CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems
Field programmable gate arrays (FPGAs) are commonly used in embedded systems. Although it is possible to reconfigure some FPGAs while an embedded system is operational, this featu...
Robert P. Dick, Niraj K. Jha