Sciweavers

7379 search results - page 1218 / 1476
» Distributed vector architectures
Sort
View
98
Voted
HPCA
2005
IEEE
16 years 3 months ago
A Unified Compressed Memory Hierarchy
The memory system's large and growing contribution to system performance motivates more aggressive approaches to improving its efficiency. We propose and analyze a memory hie...
Erik G. Hallnor, Steven K. Reinhardt
101
Voted
HPCA
2005
IEEE
16 years 3 months ago
Software Directed Issue Queue Power Reduction
The issue logic of a superscalar processor dissipates a large amount of static and dynamic power. Furthermore, its power density makes it a hot-spot requiring expensive cooling sy...
Antonio González, Jaume Abella, Michael F. ...
162
Voted
HPCA
2005
IEEE
16 years 3 months ago
A Small, Fast and Low-Power Register File by Bit-Partitioning
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
Masaaki Kondo, Hiroshi Nakamura
136
Voted
HPCA
2005
IEEE
16 years 3 months ago
SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs
Memory leaks and memory corruption are two major forms of software bugs that severely threaten system availability and security. According to the US-CERT Vulnerability Notes Datab...
Feng Qin, Shan Lu, Yuanyuan Zhou
HPCA
2005
IEEE
16 years 3 months ago
Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications
In this paper, we study the instruction cache miss behavior of four modern commercial applications (a database workload, TPC-W, SPECjAppServer2002 and SPECweb99). These applicatio...
Lawrence Spracklen, Yuan Chou, Santosh G. Abraham
« Prev « First page 1218 / 1476 Last » Next »