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ICCAD
2007
IEEE
87views Hardware» more  ICCAD 2007»
14 years 5 months ago
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
—Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is...
Philip Brisk, Ajay K. Verma, Paolo Ienne
ICCAD
2007
IEEE
124views Hardware» more  ICCAD 2007»
14 years 5 months ago
Timing budgeting under arbitrary process variations
Timing budgeting under process variations is an important step in a statistical optimization flow. We propose a novel formulation of the problem where budgets are statistical ins...
Ruiming Chen, Hai Zhou
ICCAD
2007
IEEE
96views Hardware» more  ICCAD 2007»
14 years 5 months ago
Monte-Carlo driven stochastic optimization framework for handling fabrication variability
Increasing effects of fabrication variability have inspired a growing interest in statistical techniques for design optimization. In this work, we propose a Monte-Carlo driven sto...
Vishal Khandelwal, Ankur Srivastava
ICCAD
2005
IEEE
122views Hardware» more  ICCAD 2005»
14 years 5 months ago
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
A priori wirelength estimation is concerned with predicting various wirelength characteristics before placement. In this work we propose a novel, accurate estimator of net lengths...
Andrew B. Kahng, Sherief Reda
CVPR
2010
IEEE
14 years 4 months ago
Single Image Depth Estimation From Predicted Semantic Labels
We consider the problem of estimating the depth of each pixel in a scene from a single monocular image. Unlike traditional approaches [18, 19], which attempt to map from appearanc...
Beyang Liu, Stephen Gould, Daphne Koller