173 search results - page 6 / 35 » Domain Reduction for the Circuit Constraint |
GLVLSI
2009
IEEE
14 years 8 days ago
2009
IEEE
A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution...
DATE
2000
IEEE
14 years 25 days ago
2000
IEEE
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
A rational Arnoldi method for passivity-preserving model-order reduction (MOR) with implicit multi-point moment matching for systems with frequency-dependent interconnects is desc...
FPL
2009
Springer
14 years 1 months ago
2009
Springer
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
WEBI
2010
Springer
13 years 6 months ago
2010
Springer
High-dimensional data usually incur learning deficiencies and computational difficulties. We present a novel semi-supervised dimensionality reduction technique that embeds high-dim...