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» Domain Reduction for the Circuit Constraint
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VLSID
2003
IEEE
134views VLSI» more  VLSID 2003»
14 years 8 months ago
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
Saraju P. Mohanty, N. Ranganathan
DAC
1999
ACM
14 years 9 months ago
Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints
The concept of improving the timing behavior of a circuit by relocating registers is called retiming and was first presented by Leiserson and Saxe. They showed that the problem of...
Abdallah Tabbara, Robert K. Brayton, A. Richard Ne...
DAC
1999
ACM
14 years 22 days ago
Automated Phase Assignment for the Synthesis of Low Power Domino Circuits
High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs. The problem is that domino logic comes at a...
Priyadarshan Patra, Unni Narayanan
DAC
2010
ACM
13 years 8 months ago
QuickYield: an efficient global-search based parametric yield estimation with performance constraints
With technology scaling down to 90nm and below, many yield-driven design and optimization methodologies have been proposed to cope with the prominent process variation and to incr...
Fang Gong, Hao Yu, Yiyu Shi, Daesoo Kim, Junyan Re...
COMSIS
2010
13 years 5 months ago
Effective semi-supervised nonlinear dimensionality reduction for wood defects recognition
Dimensionality reduction is an important preprocessing step in high-dimensional data analysis without losing intrinsic information. The problem of semi-supervised nonlinear dimensi...
Zhao Zhang, Ning Ye