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EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
13 years 11 months ago
Synthesis of Self-Testable Controllers
The paper presents a synthesis approach for pipelinelike controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test reg...
Sybille Hellebrand, Hans-Joachim Wunderlich
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
14 years 1 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra
IEEEPACT
2002
IEEE
14 years 15 days ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
DAC
1996
ACM
13 years 11 months ago
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
Christian Legl, Bernd Wurth, Klaus Eckl
SKG
2006
IEEE
14 years 1 months ago
Hierarchical Multicast Tree Algorithms of Data Grid
Data Grid is one of the important research subjects in the field of Grid Computing. To get a high efficiency of the system, this paper proposes a set of novel multicast algorithms...
Weijia Jia, Qingfeng Fan, Qiongli Wu, Yanxiang He