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» Drowsy Caches: Simple Techniques for Reducing Leakage Power
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GLVLSI
2008
IEEE
140views VLSI» more  GLVLSI 2008»
14 years 1 months ago
A table-based method for single-pass cache optimization
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...
Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank V...
HPCA
2009
IEEE
14 years 7 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
ICCD
2007
IEEE
100views Hardware» more  ICCD 2007»
14 years 3 months ago
VOSCH: Voltage scaled cache hierarchies
The cache hierarchy of state-of-the-art—especially multicore—microprocessors consumes a significant amount of area and energy. A significant amount of research has been devo...
Weng-Fai Wong, Cheng-Kok Koh, Yiran Chen, Hai Li
ISCAPDCS
2007
13 years 8 months ago
Evaluation of architectural support for speech codecs application in large-scale parallel machines
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
Naeem Zafar Azeemi
CISC
2009
Springer
174views Cryptology» more  CISC 2009»
13 years 4 months ago
Algebraic Side-Channel Attacks
Abstract. In 2002, algebraic attacks using overdefined systems of equations have been proposed as a potentially very powerful cryptanalysis technique against block ciphers. However...
Mathieu Renauld, François-Xavier Standaert