9 search results - page 1 / 2 » Dual-Channel Access Mechanism for Cost-Effective NoC Design |
NOCS
2008
IEEE
14 years 1 months ago
2008
IEEE
DSD
2010
IEEE
13 years 7 months ago
2010
IEEE
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
ETS
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. strate that these interconnects abstract the interconne...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
Existing work on testing NoC-based systems advocates to reuse the on-chip network itself as test access mechanism (TAM) to transport test data to/from embedded cores. While this m...