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» Dynamic Cache Switching in Reconfigurable Embedded Systems
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HPCC
2009
Springer
14 years 16 hour ago
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
Samir Ammenouche, Sid Ahmed Ali Touati, William Ja...
FPL
2008
Springer
175views Hardware» more  FPL 2008»
13 years 9 months ago
File system access from reconfigurable FPGA hardware processes in BORPH
This paper presents the design and implementation of BORPH's kernel file system layer that provides FPGA processes direct access to the general file system. Using a semantics...
Hayden Kwok-Hay So, Robert W. Brodersen
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 11 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
CASES
2001
ACM
13 years 11 months ago
Energy-efficient instruction cache using page-based placement
Energy consumption is a crucial factor in designing batteryoperated embedded and mobile systems. The memory system is a major contributor to the system energy in such environments...
Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. K...
DAC
2004
ACM
13 years 11 months ago
An SoC design methodology using FPGAs and embedded microprocessors
In System on Chip (SoC) design, growing design complexity has esigners to start designs at higher abstraction levels. This paper proposes an SoC design methodology that makes full...
Nobuyuki Ohba, Kohji Takano